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PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs ...
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Short Description: Note 1 This delay will be lengthened by 1 character time minus the last stop bit time if the transmitter interrupt delay circuit is active (See FIFO ...
Content Inside: PC16550D June 1995 PC16550D Universal Asynchronous Universal Receiver Transmitter with FIFOs General Description Features The PC16550D is an improved version of the original 16450 Y Capable of running all existing 16450 software Universal Asynchronous Receiver Transmitter (UART) Y Pin for pin compatible with the existing 16450 except Functionally identical to the 16450 on powerup (CHARAC- for CSOUT (24) and NC (29) The former CSOUT and TER mode) the PC16550D can be put into an alternate NC pins are TXRDY and RXRDY respectively Asynchronous mode (FIFO mode) to relieve the CPU of excessive software Y After reset all registers are identical to the 16450 reg- overhead ister set In this mode internal FIFOs are activated allowing 16 bytes Y In the FIFO mode transmitter and receiver are each (plus 3 bits of error data per byte in the RCVR FIFO) to be buffered with 16 byte FIFO’s to reduce the number of stored in both receive and transmit modes All the logic is on interrrupts presented to the CPU chip to minimize system overhead and maximize system ef- Y Adds or deletes standard asynchronous communication ficiency Two pin functions have been changed to allow sig- bits (start stop and parity) to or from the serial data nalling of DMA transfers Y Holding and shift registers in the 16450 Mode eliminate The UART performs serial-to-parallel conversion on data the need for precise synchronization between the CPU characters received from a peripheral device or a MODEM and serial data and parallel-to-serial conversion on data characters re- Y Independently controlled transmit receive line status ReceiverTransmitter ceived from the CPU The CPU can read the complete and data set interrupts status of the UART at any time during the functional opera- Y Programmable baud generator divides any input clock tion Status information reported includes the type and con- by 1 to (216 b 1) and generates the 16 c clock dition of the transfer operations being performed by the Y Independent receiver clock input UART as well as any error conditions (parity overrun fram- Y MODEM control functions (CTS RTS DSR DTR RI ing or break interrupt) and DCD) The UART includes a programmable baud rate generator Y Fully programmable serial-interface characteristics that is capable of dividing the timing reference clock input 5- 6- 7- or 8-bit characters by divisors of 1 to (216b1) and producing a 16 c clock for Even odd or no-parity bit generation and detection driving the internal transmitter logic Provisions are also in- 1- 1 - or 2-stop bit generation cluded to use this 16 c clock to drive the receiver logic The Baud generation (DC to 1 5M baud) UART has complete MODEM-control capability and a proc- Y False start bit detection essor-interrupt system Interrupts can be programmed to Y Complete status reporting capabilities the user’s requirements minimizing the computing required Y to handle the communications link TRI-STATE TTL drive for the data and control buses Y Line break generation and detection with The UART is fabricated using National Semiconductor’s ad- Y vanced M2CMOS process Internal diagnostic capabilities Loopback controls for communications link fault Can also be reset to 16450 Mode under software control isolation FIFOs Note This part is patented Break parity overrun framing error simulation Y Full prioritized interrupt system controls Basic Configuration TL C 8652 – 1 TRI-STATE is a registered trademark of National Semiconductor Corp C1995 National Semiconductor Corporation TL C 8652 RRD-B30M75 Printed in U S A
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